A critical issue in the design of phase-locked loops (PLLs) is the variation in PLL loop bandwidth across process, voltage and temperature (PVT) variations. For an un-modulated PLL, a decrease in this bandwidth yields a longer settling time while an increase in bandwidth translates to degraded phase noise performance. In the case of a modulated PLL, a pre-emphasis filter emulating the inverse transfer function of the PLL is typically used to ensure a flat amplitude and group delay response of a transmit chain, for example, within the bandwidth of interest. Bandwidth mismatch between the PLL and the pre-emphasis filter impacts the RMS phase error of Gaussian minimum shift key (GMSK) modulation, wherein the smaller the PLL bandwidth, the higher the impact of bandwidth mismatch. Consequently, even a relatively small variation in the PLL loop bandwidth can result in significant performance degradation. Therefore, improvements in PLL loop bandwidth calibration would be beneficial to the art.